Digital phase locked loop (PLL) circuits are well known in the art. FIG. 1 shows a block diagram of such a circuit 10. The circuit 10 receives a reference frequency signal fref that is fed to a first input of a phase difference detector (PDD) 12. A second input of the phase difference detector 12 receives a feedback frequency signal ffb. As an example, the phase difference detector 12 may comprise a bang-bang phase detector (BBPD) or a time to digital converter (TDC) based phase detector. Such phase detector circuits are well known to those skilled in the art as described, for example, by Grollitsch, et al., “A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65 nm CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2010 and Weltin-Wu, et al., “A 3 GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008 (both documents incorporated by reference). The phase difference detector 12 determines a difference in phase between the reference frequency signal fref and the feedback frequency signal ffb and outputs a digital signal Ddif indicative of that measured difference. The digital output of the phase difference detector 12 is filtered by a digital low pass filter (LPF) circuit 14 which generates a digital control signal Dcont. A digital-to-analog converter (DAC) circuit 16 converts the digital control signal Dcont to an analog control signal Acont. A control input of an oscillator (OSC) circuit 18 (such as, for example, a current controlled oscillator (CCO) or a voltage controlled oscillator (VCO)) receives the analog control signal Acont and generates an output clock signal fout having a frequency Fco that is dependent on the magnitude of the analog control signal Acont. The oscillator circuit 18 may, for example, comprise a ring oscillator circuit biased by the analog control signal Acont. A divider circuit (/N) 20 divides the output clock signal fout by N to generate the feedback frequency signal ffb which is compared to the reference frequency to control loop operation. The loop circuit accordingly operates to cause the phase of the output clock signal to lock to the phase of the reference frequency signal fref, wherein a frequency of the output clock signal is an integer multiple (N) of the reference frequency signal fref.
The digital low pass filter circuit 14 may, for example, comprise a second order filter with a proportional gain β and an integral gain α. A bandwidth compensation (BC) circuit 22 updates the value for β and α in response to the digital signal Ddif to maintain constant bandwidth of the PLL. This compensation technique is taught by Joshi, et al., “Bandwidth Compensation Technique for Digital PLL,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2016 (incorporated by reference).
FIG. 2 shows a block diagram for a digital frequency locked loop (FLL) circuit 30. A count difference (CD) circuit 32 receives a reference count Cref at a first input and a feedback count Cfb at a second input. The count difference circuit 32 is a digital circuit that operates to determine a difference in the received count values and generate a digital signal Ddif indicative of that measured difference. The digital output of the count difference circuit 32 is then filtered by a digital low pass filter (LPF) 14 to generate a digital control signal Dcont. A digital-to-analog converter (DAC) circuit 16 converts the digital control signal to an analog control signal Acont. A control input of an oscillator (OSC) circuit 18 (such as, for example, a current controlled oscillator (CCO) or a voltage controlled oscillator (VCO)) receives the analog control signal Acont and generates an output clock signal fout having a frequency Fco that is dependent on the magnitude of the analog control signal Acont. A cycle counter circuit (CCC) 34 receives the output clock signal fout and a reference frequency signal fref. The cycle counter circuit 34 operates to count a number of cycles in the output clock signal fout which occur for each single cycle of the reference frequency signal fref. That count is the feedback count Cfb which is compared to the reference count to control loop operation. The loop circuit accordingly operates to cause a frequency of the output clock signal to lock to an integer multiple of a frequency of the reference frequency signal fref, wherein the integer multiple is designated by the value of the reference count Cref.
A band-gap reference (BGR) generator circuit 24 generates a reference current iref for the digital-to-analog converter circuit 16. The digital-to-analog converter circuit 16 may, for example, comprise a current steering digital-to-analog converter circuit that responds to the digital value of the digital control signal by actuating current sources (DAC elements) that are referenced (for example, mirrored with a defined mirroring ratio) to the reference current iref. The output currents from the actuated current sources are summed to produce an output current. That output current is the analog control signal Acont if the oscillator circuit 18 is a current controlled oscillator (CCO). Alternatively, the output current is converted to a voltage for the analog control signal Acont if the oscillator circuit 18 is a voltage controlled oscillator (VCO).
The digital-to-analog converter circuit 16 must have a high-resolution in order to minimize period jitter and instantaneous phase error in the PLL 10 of FIG. 1 or minimize period jitter in the FLL 30 of FIG. 2. The resolution is given by: Kdac/Fco, where Kdac is the gain per bit in Hertz of the digital-to-analog converter circuit 16 and Fco is the frequency in Hertz of the clock signal fout output from the oscillator circuit 18. For example, if a required resolution is 0.5% in frequency and the frequency Fco is 1 GHz, a Kdac of 5 MHz is required. This leads to a requirement for 200 DAC elements, which then means that the digital-to-analog converter circuit 16 must, at minimum, be an 8-bit DAC.
Any change in Kdac or Fco will change the percentage resolution and hence the bit requirement for the digital-to-analog converter circuit 16. Considering only one output frequency point, Kdac changes with a ratio of approximately 1:2 with process (dependent on technology). So, in order to account for process variation, it is necessary to design for twice the higher resolution. Designing for the best case scenario, Kdac will have to vary between 2.5 Mhz and 5 MHz leading to a requirement for 400 DAC elements and a corresponding 9-bit DAC. Similarly for a range in the frequency Fco of 1-3 GHz, this variation would necessitate designing for almost three-times the higher resolution. So, due to variation in process and range of output frequency, the number of elements in the DAC is given by Fco(max)/Kdac(min). In the example given above, this would be 3 GHz/2.5 MHz=1200 DAC elements thus requiring an 11-bit DAC. Unfortunately, the area of the digital-to-analog converter circuit 16 increases exponentially with increase in the required number of bits and this can introduce a huge area penalty on the circuit design.
There is accordingly a need for a technique for range and process compensation that does not require larger area-occupying circuitry.